OC-3 Ethernet over SONET Mapper with Rapid Restoration (TXC-04237)


The EtherMap®-3FE is a highly integrated EoS device that provides for mapping of 10/100 Mbit/s Ethernet into SONET/SDH STS-3/STM-1 Transport payloads. The device supports connection for up to four 10/100 Mbit/s Ethernet ports, using SMII interfaces. Ethernet frames are encapsulated using either GFP, LAPS, LAPF or PPP/BCP protocol. The encapsulated Ethernet frames are then mapped into either virtually concatenated low or high order payloads, such as VT1.5 SPE/VT2 SPE/VC-11/VC-12/STS-1 SPE/VC-3, or into contiguously concatenated payloads such as STS-3c SPE/VC-4. Low and high order SONET/SDH POH generation and processing/termination is performed. A byte-wide parallel interface Telecom Bus format provides the SONET/SDH interface and may support either Drop bus or Add bus timing modes.

In addition to support for full-rate Ethernet transfer, over-subscribed Ethernet transfers are also supported using back pressure mechanisms (half and full duplex flow control) in order to prevent frame loss. External SDRAM is used for buffering Ethernet frames to support bandwidth oversubscription and flow control operation as well as receive SONET/SDH container alignment and differential delay compensation of low and high order virtually concatenated payloads.

For both low and high order virtually concatenated payloads, optional on-chip standards based LCAS processing is provided to allow hitless dynamic bandwidth adjustments.

A powerful hardware and RTOS independent EtherMap® device driver provides full access to all the features of the device through APIs. It utilizes matched get/set functions and can be easily ported.


  • Boundary scan (IEEE 1149.1 standard)
  • + 3.3V and +1.8V power supplies, 5V tolerant I/O leads
  • 400-lead plastic ball grid array package (PBGA, 27 mm x 27 mm)
  • High Order POH processing for STS-1 SPE/VC-3/STS-3c SPE/VC-4
  • Low Order POH and Pointer processing for 84/63 VT1.5/VT2/TU-11/TU-12 and 3 TU-3
  • Glueless memory interface to external 64/128/256 Mbit SDRAMs
  • Byte-wide 19 MHz parallel Add and Drop Telecom Bus interfaces
  • Per-port Ethernet side and SONET/SDH system side loopback for system level diagnostics
  • 16-bit wide microprocessor interface, selectable between Motorola or Intel
  • Dynamic bandwidth allocation using on-chip LCAS processing (ITU-T G.7042) for low and high order virtual concatenated payloads
  • Four 10/100 Mbit/s Ethernet ports, each using a SMII interface
  • Ethernet Management interface for control and configuration of externally connected PHYs
  • Provides IEEE 802.3 Half Duplex mode on 10/100 Mbit/s and Full Duplex mode on 10/100 Mbit/s Ethernet ports
  • Provides IEEE 802.3 Management Statistics (RMON)
  • Ethernet frame encapsulation/decapsulation protocols:

    • ITU-T G.7041, Generic Framing Procedure (GFP)
    • ITU-T X.86/X.85, Link Access Procedure SDH (LAPS)
    • ITU-T Q.922, Link Access Procedure Frame Mode (LAPF)
    • RFC1662/3518, PPP Bridging Control Protocol (BCP)
  • Performs mapping/demapping of encapsulated Ethernet frames into/from low order (VT1.5 SPE/VT2 SPE/VC-11/VC-12) and high order (STS-1 SPE/VC-3) virtually concatenated payloads
  • Performs mapping/demapping of encapsulated Ethernet frames into/from a single contiguous concatenated (STS-3c-SPE/VC-4) payload or a single Low/High order (VT1.5/VT2/VC-11/VC-12/STS-1/VC-3) payload

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