PHAST®-6N

Multi-Rate PHY/Framer for Telecom Networks (TXC-06306B)

Summary

The PHAST®-6N is a highly integrated SONET/SDH overhead termination device designed for TDM and EoS applications which can terminate two OC-3/STM-1 lines. Clock synthesis and clock recovery for these lines are incorporated. The device provides regenerator section and multiplex section (line) overhead processing, high-order (AU-3/AU-4/STS-1/STS-3c) pointer tracking and retiming and SPE path overhead processing and performance monitoring. It is a powerful solution for single or dual OC-3 telecom applications, especially those requiring high-order ring closure and carrier-grade protection capability. PHAST®-6N also provides a full 18 x 18 non-blocking STS-1 level cross connect, allowing line/path (UPSR/SNCP) protection. An APS line port may be utilized for applications such as MSP 1+1, 1:1, and 1:n architectures.

The PHAST®-6N is designed to interface directly with the EtherMap®-3 Pt and EtherMap®-12 Ethernet mappers for EoS applications as well as the VTXPTM cross connect with TU/VT processing. The software driver contains independent modules that allow the user to compile only relevant required components, a considerable resource savings. The function of the API's driver is to configure, control and manage the PHAST®-6N device as well as collect and deliver fault and performance monitoring data to the host.

Features

  • Hardware: Bit-serial Line Interfaces
  • Hardware: Integrated Clock, Data Recovery, Clock Synthesis
  • Hardware: 1+1, 1:1 and 1:n APS for two OC-3/STM-1 Signals
  • Hardware: TOH, POH Processing, Generation Functions
  • Hardware: High-order Pointer Tracker/Retiming, Performance Monitor
  • Hardware: Dedicated Overhead Byte Interface
  • Hardware: High-order 18 x 18 Cross Connect (STS-1/STM-0 Level)
  • Hardware: High-order Path, Line Loopbacks
  • Software: API-based Device Driver
  • Data Path: 2 x 155 Mbps LVPECL, 622 Mbps LVDS APS (Serial)
  • Data Path: 77 MHz Telecom Bus
  • Data Path: Line and Path Alarm Indication Ports (Ring)
  • Microprocessor: Intel/Motorola Compatible (16-Bit Data)
  • Other: JTAG Boundary Scan (IEEE JTAG™)


Diagram

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